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The SCL clock signal generated by the I C master determines maximum transmission rate on the bus.
I C Maximum Transmission Rate
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I2Cn_CTRL must be reset. This should be done regardless whether the slave is going to be re-enabled
or not.
15.3.4 Clock Generation
2
The clock is generated as a division of the peripheral clock, and is given by Equation 15.2 (p. 149) :
2
f SCL = f HFPERCLK /(((N low + N high ) x (DIV + 1)) + 4)
(15.2)
I C High and Low Cycles Equations
N low and N high specify the number of prescaled clock cycles in the low and high periods of the clock
signal respectively. The worst case low and high periods of the signal are:
2
T high = (N high x (DIV + 1) + 3)/f HFPERCLK
T low = (N low x (DIV + 1)+ 3)/f HFPERCLK
(15.3)
149) along with the highest I C-bus frequencies in the given modes that can be achieved without
violating the timing specifications of the I C-bus. The frequencies are calculated taking the maximum
Table 15.2. I C Clock Modes
The values of N low and N high and thus the ratio between the high and low parts of the clock signal is
controlled by CLHR in the I2Cn_CTRL register. The available modes are summarized in Table 15.2 (p.
2
2
allowed rise and fall times of SDA and SCL into account. Higher frequencies may be achieved in
practice. The 3 extra cycles are synchronization, and must be taken into consideration when DIV in the
I2Cn_CLKDIV register has a low value.
Note
DIV must be 1 or higher when slave is enabled.
2
Mode
CLHR
N low : N high
Sm max
Fm max
Fm+ max
frequency
frequency
frequency
STANDARD
ASYMMETRIC
FAST
0
1
2
4:4
6:3
11:6
93 kHz
75 kHz
79 kHz
313 kHz
392 kHz
383 kHz
806 kHz
980 kHz
987 kHz
arbitration is enabled, the value on SDA is sensed after each time the I C module attempts to change
its value. If the sensed value is different than the value the I C module tried to output, it is interpreted as
a simultaneous transmission by another device, and the I C module has lost arbitration.
and the I C device goes idle. If an I C master loses arbitration during the transmission of an address,
15.3.5 Arbitration
Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When
2
2
2
Whenever arbitration is lost, the ARBLOST interrupt flag in I2Cn_IF is set, any lines held are released,
2 2
another master may be trying to address it. The master therefore receives the rest of the address, and
if the address matches the slave address of the master, the master goes into either slave transmitter
or slave receiver mode.
Note
Arbitration can be lost both when operating as a master and when operating as a slave.
2011-04-12 - d0001_Rev1.10
149
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